View X28HC256SIZ-90_6600764.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

worldwide corporate headquarters 16 malcolm hoyt drive . newburyport, ma 01950 phone 978.462.9332 . email sales@rocelec.com . web www.rocelec.com ? rochester electronics, llc - all rights reserved - 11162012 C n ew p roduct i ntroduction C x28hc256dm-12 rochester electronics has re-introduced and continues to manufacture critically needed semiconductors with the full authorization of the original manufacturer and an attention to quality that meets or exceeds the original component. x28hc256dm-12 original part number: x28hc256dm-12 description: 256k eeprom package: 28 pin dip manufacturing flow: mto endurance: 1,000,000 cycles available in pb-free versions x28hc256d-12 x28hc256d-90 x28hc256di-15 x28hc256dmb-15 x28hc256ei-12 related devices [ by temperature / package type / speed / application ] original manufacturer: low power cmos eeprom with hi-speed page write capability the x28hc256 is a second generation high performance cmos 32k x 8 eeprom. it is fabricated with intersils proprietary, textured poly foating gate technology, providing a highly reliable 5v only nonvolatile memory. the x28hc256 supports a 128- byte page write operation, efectively providing a 24s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. the x28hc256 also features data polling and toggle bit polling, two methods of providing early end of write detection. re-introduced by rochester electronics on october, 31, 2012 x28hc256fm-90 x28hc256jm-15t1 x28hc256ki-15 x28hc256pm-12 x28hc256kmb-15
1 ? fn8108.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. x28hc256 256k, 32k x 8-bit 5v, byte alterable eeprom the x28hc256 is a second generation high performance cmos 32k x 8 eeprom. it is fabricated with intersil?s proprietary, textured poly floating gate technology, providing a highly reliable 5v only nonvolatile memory. the x28hc256 supports a 128-byte page write operation, effectively providing a 24s/byte write cycle, and enabling the entire memory to be typica lly rewritten in less than 0.8 seconds. the x28hc256 also features data polling and toggle bit polling, two methods of providing early end of write detection. the x28hc256 also supports the jedec standard software data protection feature for protecting against inadvertent writes during power-up and power-down. endurance for the x28hc256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years. features ? access time: 70ns ? simple byte and page write - single 5v supply - no external high voltages or v p-p control circuits - self-timed - no erase before write - no complex programming algorithms - no overerase problem ? low power cmos - active: 60ma - standby: 500a ? software data protection - protects data against system level inadvertent writes ? high speed page write capability ? highly reliable direct write ? cell - endurance: 1,000,000 cycles - data retention: 100 years ? early end of write detection - data polling - toggle bit polling ? pb-free plus anneal available (rohs compliant) block diagram x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 256kbit eeprom array i/o 0 to i/o 7 data inputs/outputs ce oe v cc v ss a 0 to a 14 we address inputs data sheet may 7, 2007
2 fn8108.2 may 7, 2007 ordering information part number part marking access time (ns) temp. range (c) package pkg. dwg. # x28hc256di-15 x28hc256di-15 rr 150 -40 to +85 28 ld cerdip f28.6 x28hc256dm-15 x28hc256dm-15 rr -55 to +125 28 ld cerdip f28.6 x28hc256dmb-15 c x28hc256dmb-15 mil-std-883 28 ld cerdip f28.6 x28hc256emb-15 c x28hc256emb-15 mil-std-883 32 ld lcc (458 mils) x28hc256fmb-15 c x28hc256fmb-15 mil-std-883 28 ld flatpack (440 mils) x28hc256j-15*, ** x28hc256j-15 rr 0 to +70 32 ld plcc n32.45x55 x28hc256jz-15* (note) x28hc256j-15 zrr 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc256ji-15*, ** x28hc256ji-15 rr -40 to +85 32 ld plcc n32.45x55 x28hc256jiz-15* (note) x28hc256ji-15 zrr -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc256jm-15* x28hc256jm-15 rr -55 to +125 32 ld plcc n32.45x55 x28hc256ki-15 x28hc256ki-15 rr -40 to +85 28 ld pga g28.550x650a x28hc256km-15 x28hc256km-15 rr -55 to +125 28 ld pga g28.550x650a x28hc256kmb-15 c x28hc256kmb-15 mil-std-883 28 ld pga g28.550x650a x28hc256p-15 x28hc256p-15 rr 0 to +70 28 ld pdip e28.6 x28hc256pz-15 (note) x28hc256p-15 rrz 0 to +70 28 ld pdip (pb-free)*** e28.6 x28hc256pi-15 x28hc256pi-15 rr -40 to +85 28 ld pdip e28.6 x28hc256piz-15 (note) x28hc256pi-15 rrz -40 to +85 28 ld pdip (pb-free)*** e28.6 x28hc256pm-15 x28hc256pm-15 rr -55 to +125 28 ld pdip e28.6 x28hc256si-15* x28hc256si-15 rr -40 to +85 28 ld soic (300 mil) mdp0027 x28hc256siz-15* (note) x28hc256si-15 rrz -40 to +85 28 ld soic (300 mil) (pb-free) mdp0027 x28hc256sm-15 x28hc256sm-15 rr -55 to +125 28 ld soic (300 mil) mdp0027 x28hc256d-12 x28hc256d-12 rr 120 0 to +70 28 ld cerdip (520 mils) f28.6 x28hc256di-12 x28hc256di-12 rr -40 to +85 28 ld cerdip (520 mils) f28.6 x28hc256dm-12 x28hc256dm-12 rr -55 to +125 28 ld cerdip (520 mils) f28.6 x28hc256dmb-12 c x28hc256dmb-12 mil-std-883 28 ld cerdip (520 mils) f28.6 x28hc256ei-12 x28hc256ei-12 rr -40 to +85 32 ld lcc (458 mils) x28hc256em-12 x28hc256em-12 rr -55 to +125 32 ld lcc (458 mils) x28hc256emb-12 c x28hc256emb-12 mil-std-883 32 ld lcc (458 mils) x28hc256fmb-12 c x28hc256fmb-12 mil-std-883 28 ld flatpack (440 mils) x28hc256j-12* x28hc256j-12 rr 0 to +70 32 ld plcc n32.45x55 x28hc256jz-12* (note) x28hc256j-12 zrr 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc256ji-12* x28hc256ji-12 rr -40 to +85 32 ld plcc n32.45x55 x28hc256jiz-12* (note) x28hc256ji-12 zrr -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc256ki-12 x28hc256ki-12 rr -40 to +85 28 ld pga g28.550x650a x28hc256km-12 x28hc256km-12 rr -55 to +125 28 ld pga g28.550x650a x28hc256kmb-12 c x28hc256kmb-12 mil-std-883 28 ld pga g28.550x650a x28hc256p-12 x28hc256p-12 rr 0 to +70 28 ld pdip e28.6 x28hc256pz-12 (note) x28hc256p-12 rrz 0 to +70 28 ld pdip (pb-free)*** e28.6 x28hc256pi-12 x28hc256pi-12 rr -40 to +85 28 ld pdip e28.6 x28hc256
3 fn8108.2 may 7, 2007 x28hc256piz-12 (note) x28hc256pi-12 rrz -40 to +85 28 ld pdip (pb-free)*** e28.6 x28hc256s-12* x28hc256s-12 rr 120 0 to +70 28 ld soic (300 mils) mdp0027 x28hc256sz-12 (note) x28hc256s-12 rrz 0 to +70 28 ld soic (300 mils) (pb-free) mdp0027 x28hc256si-12* x28hc256si-12 rr -40 to +85 28 ld soic (300 mils) mdp0027 x28hc256siz-12 (note) x28hc256si-12 rrz -40 to +85 28 ld soic (300 mils) (pb-free) mdp0027 x28hc256sm-12*, ** x28hc256sm-12 rr -55 to +125 28 ld soic (300 mils) mdp0027 x28hc256d-90 x28hc256d-90 rr 90 0 to +70 28 ld cerdip (520 mils) f28.6 x28hc256di-90 x28hc256di-90 rr -40 to +85 28 ld cerdip (520 mils) f28.6 x28hc256dm-90 x28hc256dm-90 rr -55 to +125 28 ld cerdip (520 mils) f28.6 x28hc256dmb-90 c x28hc256dmb-90 mil-std-883 28 ld cerdip (520 mils) f28.6 x28hc256em-90 x28hc256em-90 rr -55 to +125 32 ld lcc (458 mils) x28hc256emb-90 c x28hc256emb-90 mil-std-883 32 ld lcc (458 mils) x28hc256fi-90 x28hc256fi-90 rr -40 to +85 28 ld flatpack (440 mils) x28hc256fm-90 x28hc256fm-90 rr -55 to +125 28 ld flatpack (440 mils) x28hc256fmb-90 c x28hc256fmb-90 mil-std-883 28 ld flatpack (440 mils) x28hc256j-90* x28hc256j-90 rr 0 to +70 32 ld plcc n32.45x55 x28hc256jz-90* (note) x28hc256j-90 zrr 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc256ji-90* x28hc256ji-90 rr -40 to +85 32 ld plcc n32.45x55 x28hc256jiz-90* (note) x28hc256ji-90 zrr -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc256jm-90* x28hc256jm-90 rr -55 to +125 32 ld plcc n32.45x55 x28hc256km-90 x28hc256km-90 rr -55 to +125 28 ld pga g28.550x650a x28hc256kmb-90 c x28hc256kmb-90 mil-std-883 28 ld pga g28.550x650a x28hc256p-90 x28hc256p-90 rr 90 0 to +70 28 ld pdip e28.6 x28hc256pz-90 (note) x28hc256p-90 rrz 0 to +70 28 ld pdip (pb-free)*** e28.6 x28hc256pi-90 x28hc256pi-90 rr -40 to +85 28 ld pdip e28.6 x28hc256piz-90 (note) x28hc256pi-90 rrz -40 to +85 28 ld pdip (pb-free)** e28.6 x28hc256s-90* x28hc256s-90 rr 0 to +70 28 ld soic (300 mils) mdp0027 x28hc256si-90* x28hc256si-90 rr -40 to +85 28 ld soic (300 mils) mdp0027 X28HC256SIZ-90 (note) x28hc256si-90 rrz -40 to +85 28 ld soic (300 mils) (pb-free) mdp0027 x28hc256si-20t1 200 -40 to +85 28 ld soic (300 mils) tape and reel mdp0027 *add "t1" suffix for tape and reel. **add "t2" suffix for tape and reel. ***pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proce ssing applications. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking access time (ns) temp. range (c) package pkg. dwg. # x28hc256
4 fn8108.2 may 7, 2007 pinouts pin descriptions addresses (a 0 to a 14 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power consumption is reduced. output enable (oe ) the output enable input controls the data output buffers, and is used to initiate read operations. data in/data out (i/o 0 to i/o 7 ) data is written to or read from the x28hc256 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the x28hc256. x28hc256 (28 ld cerdip, flatpack, pdip, soic) top view x28hc256 (32 ld plcc, lcc) top view x28hc256 (28 ld pga) bottom view a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28hc256 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 a 9 a 11 nc oe a 10 ce i/o 7 i/o 6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a 7 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 a 12 a 14 nc v cc we a 13 nc x28hc256 11 i/o 0 10 a 0 14 v ss 9 a 1 8 a 2 7 a 3 6 a 4 5 a 5 2 a 12 28 v cc 12 i/o 1 13 i/o 2 15 i/o 3 4 a 6 3 a 7 1 16 i/o 4 20 ce 22 oe 24 a 9 17 i/o 5 27 we 19 i/o 7 21 a 10 23 a 11 25 a 8 18 i/o 6 26 a 13 a 14 x28hc256 x28hc256
5 fn8108.2 may 7, 2007 device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control ar chitecture eliminates bus contention in a system environ ment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28hc256 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs fi rst. a byte write operation, once initiated, will automatically continue to completion, typically within 3ms. page write operation the page write feature of the x28hc256 allows the entire memory to be written in typically 0.8 seconds. page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the x28hc256, prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 7 through a 14 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following t he initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. each successive byte load cycle, started by the we high to low transition, must begin within 100s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100s, the internal automatic programming cycle will commen ce. there is no page write window limitation. effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte l oad cycle time of 100s. write operation status bits the x28hc256 provides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. data polling (i/o 7 ) the x28hc256 features data polling as a method to indicate to the host system th at the byte write or page write cycle has completed. data polling allows a simple bit test operation to determine the status of the x28hc256. this eliminates additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on i/o 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. toggle bit (i/o 6 ) the x28hc256 also provides another method for determining when the internal write cycle is complete. during the internal programming cycle i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations. pin names symbol description a 0 to a 14 address inputs i/o 0 to i/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect 5 tb dp 43210 i/o reserved toggle bit data polling figure 1. status bit assignment x28hc256
6 fn8108.2 may 7, 2007 data polling i/o 7 data polling can effectively halve the time for writing to the x28hc256. the timing diagram in figure 2 illustrates the sequence of events on the bus. the software flow diagram in figure 3 illustrates one method of implementing the routine. ce oe we i/o 7 x28hc256 ready last write high z v ol v ih a 0 to a 14 an an an an an an v oh an figure 2. data polling bus sequence write data save last data and address read last address io 7 compare? x28hc256 no yes writes complete? no yes ready figure 3. data polling software flow x28hc256
7 fn8108.2 may 7, 2007 the toggle bit i/o 6 ? the toggle bit can eliminate the chore of saving and fetching the last address and data in order to implement data polling. this can be especially helpful in an array comprised of multiple x28hc256 memories that is frequently updated. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software flow diagram in figure 5 illustrates a method for polling the toggle bit. hardware data protection the x28hc256 provides two hardware features that protect nonvolatile data from inadvertent writes. ? default v cc sense?all write functions are inhibited when v cc is 3.5v typically. ? write inhibit?holding either oe low, we high, or ce high will prevent an inadvert ent write cycle during power- up and power-down, maintaining data integrity. software data protection the x28hc256 offers a software-controlled data protection feature. the x28hc256 is sh ipped from intersil with the software data protection not enabled; that is, the device will be in the standard operating mode. in this mode data should be protected during power-up/down operations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28hc256 can be automatically protected during power-up and power-down (without the need for external circuits) by employing the software data protection feature. the internal software data protection circuit is enabled after the first write operatio n, utilizing the software algorithm. this circuit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28hc256 is also protected from inadvertent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. ce oe we x28c512, x28c513 last write i/o 6 high z * * v oh v ol ready * i/o 6 beginning and ending state of i/o 6 will vary. figure 4. toggle bit bus sequence compare x28c256 no yes ok? compare accum with addr n load accum from addr n last write ready yes figure 5. toggle bit software flow x28hc256
8 fn8108.2 may 7, 2007 software algorithm selecting the software data protection mode requires the host system to precede data writ e operations by a series of three write operations to three specific addresses. refer to figure 6 and 7 for the sequence. the three-byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. once the page load cycle has been co mpleted, the device will automatically be returned to the data protected state. software data protection regardless of whether the device has previously been protected or not, once the soft ware data protection algorithm is used and data has been written, the x28hc256 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the x28hc256 will be write prot ected during power-down and after any subsequent power-up. note: once initiated, the sequence of write operations should not be interrupted. ce we (v cc ) write protected v cc 0v data address aaa 5555 55 2aaa a0 5555 t blc max writes ok byte or age t wc figure 6. timing sequence?byte or page write write last write data xx to any write data a0 to address 5555 write data 55 to address 2aaa write data aa to address 5555 after t wc re-enters data protected state byte to last address address optional byte/page load operation byte/page load enabled figure 7. write sequence for software data x28hc256
9 fn8108.2 may 7, 2007 resetting software data protection in the event the user wants to deactivate the software data protection feature for test ing or reprogramming in an eeprom programmer, the following six step algorithm will reset the internal protection circuit. after t wc , the x28hc256 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. system considerations because the x28hc256 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power di ssipation, and eliminate the possibility of contention where multiple i/o pins share the same bus. to gain the most benefit, it is recommended that ce be decoded from the address bus and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. because the x28hc256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of the l/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recommended that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capaci tor may have to be larger. in addition, it is recommended th at a 4.7f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. ce we standard operating mode v cc data address aaa 5555 55 2aaa 80 5555 t wc aa 5555 55 2aaa 20 5555 figure 8. reset software data protection timing sequence write data 55 to address 2aaa write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555 after t wc , re-enters unprotected state figure 9. write sequence for resetting software x28hc256
10 fn8108.2 may 7, 2007 absolute maximum rati ngs thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . . .-10c to +85c x28hc256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +135c x28hc256i, x28hc256m . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . . -1v to +7v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . commerical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc electrical specifications over recommended oper ating conditions, unless otherwise specified. parameter symbol test conditions limits unit min typ (note 7) max v cc active current (ttl inputs) i cc ce = oe = v il , we = v ih , all i/o?s = open, address inputs = .4v/2.4v levels @ f = 10mhz 30 60 ma v cc standby current (ttl inputs) i sb1 ce = v ih , oe = v il , all i/o?s = open, other inputs = v ih 12ma v cc standby current (cmos inputs) i sb2 ce = v cc - 0.3v, oe = gnd, all i/os = open, other inputs = v cc - 0.3v 200 500 a input leakage current i li v in = v ss to v cc 10 a output leakage current i lo v out = v ss to v cc , ce = v ih 10 a input low voltage v ll (note 2) -1 0.8 v input high voltage v ih (note 2) 2 v cc + 1 v output low voltage v ol i ol = 6ma 0.4 v output high voltage v oh i oh = -4ma 2.4 v notes: 1. typical values are for t a = +25c and nominal supply voltage. 2. v il min. and v ih max. are for reference only and are not tested. power-up timing parameter symbol max unit power-up to read t pur , note 3 100 s power-up to write t puw , note 3 5 ms note: 3. this parameter is periodically sampled and not 100% tested. x28hc256
11 fn8108.2 may 7, 2007 equivalent ac load circuit symbol table capacitance t a = +25c, f = 1mhz, v cc = 5v. symbol test conditions max unit c i/o (note 9) input/output capacitance v i/o = 0v 10 pf c in (note 9) input capacitance v in = 0v 6 pf endurance and da ta retention parameter min max unit endurance 1,000,000 cycles data retention 100 years ac conditions of test input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v mode selection ce oe we mode i/o power l l h read d out active lhl write d in active h x x standby and write inhibit high z standby x l x write inhibit ? ? x x h write inhibit ? ? 5v 1.92k 30pf output 1.37k waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x28hc256
12 fn8108.2 may 7, 2007 read cycle notes: 4. t lz min., t hz , t olz min. and t ohz are periodically sampled and not 100% tested, t hz and t ohz are measured with c l = 5pf, from the point when ce , oe return high (whichever occurs first) to the time when the outputs are no longer driven. 5. for faster 256k products, refer to x28vc256 product line. ac electrical specifications over recommended operating conditions, unless otherwise specified. parameter symbol x28hc256-70 x28hc256-90 x28hc256-12 x28hc256-15 unit min max min max min max min max read cycle time t rc (note 5) 70 90 120 150 ns chip enable access time t ce (note 5) 70 90 120 150 ns address access time t aa (note 5) 70 90 120 150 ns output enable access time t oe 35 40 50 50 ns ce low to active output t lz (note 4) 0 0 0 0 ns oe low to active output t olz (note 4) 0 0 0 0 ns ce high to high z output t hz (note 4) 35 40 50 50 ns oe high to high z output t ohz (note 4) 35 40 50 50 ns output hold from address change t oh 000 0ns t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid x28hc256
13 fn8108.2 may 7, 2007 we controlled write cycle write cycle limits parameter symbol min typ (note 6) max unit write cycle time t wc (note 7) 3 5 ms address setup time t as 0ns address hold time t ah 50 ns write setup time t cs 0ns write hold time t ch 0ns ce pulse width t cw 50 ns oe high setup time t oes 0ns oe high hold time t oeh 0ns we pulse width t wp 50 ns we high recovery (page write only) t wph (note 8) 50 ns data valid t dv 1s data setup t ds 50 ns data hold t dh 0ns delay to next write after polling is true t dw (note 8) 10 s byte load cycle t blc 0.15 100 s notes: 6. typical values are for t a = +25c and nominal supply voltage. 7. t wc is the minimum cycle time to be allow ed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. 8. t wph and t dw are periodically sampled and not 100% tested. address t as t wc t ah t oes t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp x28hc256
14 fn8108.2 may 7, 2007 ce controlled write cycle page write cycle notes: 9. between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. 10. the timings shown above are unique to page write operations. i ndividual byte load operations within the page write must conf orm to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t cs t ds t dh t ch ce we oe data in data out high z data valid t cw we oe last byte byte 0 byte 1 byte 2 byte n byte n + 1 byte n + 2 t wp t wph t blc t wc ce address i/o *for each successive write with in the page write operation, a 7 to a 15 should be the same or writes to an unknown address could occur. (note 10) (note 9) x28hc256
15 fn8108.2 may 7, 2007 data polling timing diagram (note 11) toggle bit timing diagram (note 11) note: 11. polling operations are by defin ition read cycles and are therefor e subject to read cycle timings. address a n d in = x t wc t oeh t oes ce we oe i/o 7 t dw a n a n d out = x d out = x ce oe we i/o 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary, depending upon actual t wc . x28hc256
16 fn8108.2 may 7, 2007 x28hc256 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f28.6 mil-std-1835 gdip1-t28 (d-10, configuration a) 28 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.490 - 37.85 5 e 0.500 0.610 12.70 15.49 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n28 288 rev. 0 4/94
17 fn8108.2 may 7, 2007 x28hc256 plastic leaded chip carrier packages (plcc) a1 a seating plane 0.015 (0.38) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 pin (1) c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l ne nd identifier (0.12) m ds - b s as 0.042 (1.07) 0.048 (1.22) 0.005 n32.45x55 (jedec ms-016ae issue a) 32 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.125 0.140 3.18 3.55 - a1 0.060 0.095 1.53 2.41 - d 0.485 0.495 12.32 12.57 - d1 0.447 0.453 11.36 11.50 3 d2 0.188 0.223 4.78 5.66 4, 5 e 0.585 0.595 14.86 15.11 - e1 0.547 0.553 13.90 14.04 3 e2 0.238 0.273 6.05 6.93 4, 5 n28 286 nd 7 7 7 ne 9 9 7 rev. 0 7/98 notes: 1. controlling dimension: inch . converted millimeter dimen- sions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. al- lowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are mea- sured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. 7. nd denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. ne denotes the num- ber of leads on the two long sides of the package. -c-
18 fn8108.2 may 7, 2007 x28hc256 ceramic pin grid array package (cpga) g28.550x650a 28 lead ceramic pin grid array package rev. 0 12/05 0.561 (14.25) 0.541 (13.75) note: all dimensions in inches (in parentheses in millimeters). 0.020 (0.51) 0.016 (0.41) 12 13 15 17 18 11 10 14 16 19 9 8 20 21 7 6 22 23 5 2 28 24 25 4 3 1 27 26 typ. 0.100 (2.54) all leads 0.080 (2.03) 4 corners 0.070 (1.78) pin 1 index 0.660 (16.76) 0.640 (16.26) 0.110 (2.79) 0.090 (2.29) 0.072 (1.83) 0.062 (1.57) 0.185 (4.70) 0.175 (4.44) 0.050 (1.27) 0.008 (0.20) a a a a note: leads 4, 12, 18, and 26 0.080 (2.03) 0.070 (1.78)
19 fn8108.2 may 7, 2007 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994 x28hc256
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8108.2 may 7, 2007 x28hc256 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00

▲Up To Search▲

Price & Availability of X28HC256SIZ-90

	To Download X28HC256SIZ-90 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .